Devices in a semiconductor die exhibit variations in behavior within the die. These variations include channel length variations and threshold voltage variations in transistors. Such variations are called within-die variations. As a result of such variations, two devices of identical dimensions on the same die may exhibit different behavior (e.g., current drive strength, turn-on and turn-off characteristics, output signal swing, jitter tolerance, etc.) depending on the location of the devices on the die.
For example, one end of a die (also called a processor or a chip) may have devices that behave faster than identical devices of identical dimensions on the other end of the same die. Such variation in the device behavior may be classified as systematic variation and random variation. The systematic variation is generally predictable or repeatable and may be reduced by well known methods such as matching and nesting layout techniques of the devices. However, random variation by definition is unpredictable and may not be reduced by matching and nesting layout techniques alone.
Such variations within a die cause large variations in performance parameters of the die, for example, output signal swings of an input-output (I/O) transmitter in an I/O lane of an I/O system. I/O transmitters are generally situated on the edges of a die. The edges may be long edges e.g., 5000 μm from one end of the edge to the other end of the edge. As mentioned above, one end of an edge of the die may have devices that behave faster or slower than the identical devices on the other end of the edge of the same die. As a result of such wide variations in behavior along the same edge of the die, an I/O transmitter of an I/O lane on one end of an edge of the die may generate output signal swings that are higher or lower than an identical I/O transmitter of another I/O lane on the other end of the same edge. Consequently, receivers for the signals transmitted by such I/O transmitters receive signals of varying swings which may impact the timing budget of the I/O system.
FIG. 1A illustrates an I/O system 100 having a processor 110 communicatively coupled with a receiver 106 via an interconnect 105. The processor 110 includes a traditional centralized current reference generator (ICOMP) 101 to provide compensated bias current to each set of I/O transmitters (e.g., 107) from a plurality of sets of I/O transmitters 107-109. The ICOMP 101 is used to compensate variations in output signal swings generated by each I/O transmitter by controlling the current used by each I/O transmitter (e.g., 104) via its bias generator 103 to generate the output signal swing on the interconnect 105. The bias current generated by the centralized ICOMP is distributed in the die 110 via current mirroring circuits 102 to each I/O transmitter 104 along the edge of the die 110. Due to large current distribution networks to distribute the bias currents from the centralized ICOMP, local layout techniques to reduce the impact of within-die variations such as nesting, inter-digitation, and matching cannot be used to ensure that the entire distribution network of current mirrors generate the same bias current for every I/O transmitter—to apply the local layout techniques all current mirrors must be inter-digitated with each other which cannot be done practically when the current mirrors are not close to one another or when the current mirrors do not abut one another.
Consequently, the bias current generated by the ICOMP and transmitted to each I/O transmitter via the distribution network has different current values from one end of the edge of the die to the other end of the edge of the same die. These different values of the bias current caused by the within-die variations of the distributed network, including current mirror circuits 102 and bias generators 103, result in I/O lane to lane variations in output signal swings.
FIG. 1B is a transistor level traditional ICOMP scheme 120 to show a number of transistors that contribute to the within-die variations in the output signal swing of each transmitter of a plurality of transmitters. The ICOMP scheme 120 includes the ICOMP generator 101 to generate a compensated bias current which is distributed by current mirrors (e.g., 102) to each I/O transmitter (e.g., 103) having a local bias generator with transistors M5-M7 and the transmitter driver 104. In this traditional ICOMP scheme 120, at least 10 transistors, M1-M10, contribute to variations in the output signal swings between the transmitters. These within-die variations can be very large e.g., +/−80% variations in output signal swings between the I/O transmitter lanes. As mentioned above, transistors M9 and M10 cannot take advantage of local layout techniques to reduce spatial mismatches because they are not next to each other i.e., they are not abutting each other. In some instances where transistors M1-M8 are very close to one another, they can use layout techniques such as nesting to eliminate spatial effects but random mismatches are still present in each of the transistors and such random mismatches are additive with respect to within-die variations. Consequently, transistors M1-M10 may aggregate the effect of within-die variations on the output signal swing of the I/O transmitters.